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74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) product specification supersedes data of 1995 aug 17 ic23 data handbook 1998 feb 27 integrated circuits
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 2 1998 feb 27 853-1782 19026 features ? independent registers for a and b buses ? multiple v cc and gnd pins minimize switching noise ? live insertion/extraction permitted ? powerup 3-state ? powerup reset ? multiplexed real-time and stored data ? outputs sink 64ma and source 32ma ? latchup protection exceeds 500ma per jedec std 17 ? 74abth16646 incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model description the 74ABT16646 highperformance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74ABT16646 16-bit transceiver/register consists of two sets of bus transceiver circuits with 3-state outputs, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus will be clocked into the registers as the appropriate clock pin goes high. output enable (noe ) and direction (ndir) pins are provided to control the transceiver function. in the transceiver mode, data present at the high impedance port may be stored in either the a or b register or both. the select (nsab, nsba) pins determine whether data is stored or transferred through the device in real-time. the ndir determines which bus will receive data when the noe is active low. in the isolation mode (noe = high), data from bus a may be stored in the b register and/or data from bus b may be stored in the a register. when an output function is disabled, the input function is still enabled and may be used to store and transmit data. only one of the two buses, a or b may be driven at a time. two options are available, 74ABT16646 which does not have the bus-hold feature and 74abth16646 which incorporates the bus-hold feature. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0v typical unit t plh t phl propagation delay nax to nbx c l = 50pf; v cc = 5v 3.3 2.7 ns c in input capacitance v i = 0v or v cc 3 pf c i/o i/o capacitance v o = 0v or v cc ; 3-state 7 pf i cc quiescent su pp ly current outputs disabled; v cc =5.5v 550 m a i ccz q u iescent s u ppl y c u rrent outputs low; v cc =5.5v 9 ma ordering information packages temperature range outside north america north america dwg number 56-pin plastic ssop type iii 40 c to +85 c 74ABT16646 dl bt16646 dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74ABT16646 dgg bt16646 dgg sot364-1 56-pin plastic ssop type iii 40 c to +85 c 74abth16646 dl bh16646 dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74abth16646 dgg bh16646 dgg sot364-1 pin description pin number symbol name and function 2, 55, 27, 30 1cpab, 1cpba, 2cpab, 2cpba clock input a to b / clock input b to a 3, 54, 26, 31 1sab, 1sba, 2sab, 2sba select input a to b / select input b to a 1, 28 1dir, 2dir direction control inputs 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24 1a0 1a7, 2a0 2a7 data inputs/outputs (a side) 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33 1b0 1b7, 2b0 2b7 data inputs/outputs (b side) 56, 29 1oe , 2oe output enable inputs 4, 11, 18, 25, 32, 39, 46, 53 gnd ground (0v) 7, 22, 35, 50 v cc positive supply voltage
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 3 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 27 28 30 29 1dir 1cpab 1sab gnd 1a0 1a1 1a2 1a3 1a4 gnd 1a5 1a6 1a7 2a0 2a2 gnd 2a3 v cc 2a1 2a4 2a5 2a6 2a7 2sab v cc gnd 2cpab 2dir 1oe 1cpba 1sba gnd 1b0 1b1 1b2 1b3 1b4 gnd 1b5 1b6 1b7 2b0 2b2 gnd 2b3 v cc 2b1 2b4 2b5 2b6 2b7 2sba v cc gnd 2cpba 20e sh00026 function table inputs data i/o operating mode noe ndir ncpab ncpba nsab nsba nax nbx operating mode x x x x x input unspecified output* store a, b unspecified x x x x x unspecified output* input store b, a unspecified h h x x h or l h or l x x x x input input store a and b data isolation, hold storage l l l l x x x h or l x x l h output input real time b data to a bus stored b data to a bus l l h h x h or l x x l h x x input output real time a data to b bus stored a data to b bus h = high voltage level l = low voltage level x = don't care = low-to-high clock transition * the data output function may be enabled or disabled by various signals at the noe input. data input functions are always enabled, i.e., data at the bus pins will be stored on every lowtohigh transition of the clock.
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 4 logic symbol (ieee/iec) 3 en1 [ba] sh00025 1 28 30 29 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 6d 2 56 55 27 g3 c4 g7 26 3 en2 [ab] g5 c6 g10 10 en8 [ba] 10 en9 [ab] c11 g12 c13 g14 1 ? 1 7 17 54d 5 1 1 2 ? 1 ? 8 13d 14 114 1 9 ? 12 11d 12 1 1oe 1dir 1cpba 1sba 1cpab 1sab 2oe 2dir 2cpba 2sba 2cpab 2sab 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 logic symbol 2 3 1cpab 1sab 1 1dir 55 1cpba 27 26 2cpab 2sab 28 2dir 30 2cpba 54 1sba 56 1oe 31 2sba 29 2oe 5 9 10 12 13 14 68 52 51 49 48 47 45 44 43 15 16 17 19 20 21 23 24 42 41 40 38 37 36 34 33 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 sh00027
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 5 the following examples demonstrate the four fundamental bus-management functions that can be performed with the 74ABT16646. } real time bus transfer bus b to bus a noe ndir ncpab ncpba nsab nsba llxxxl } real time bus transfer bus a to bus b noe ndir ncpab ncpba nsab nsba lh x x lx } storage from a, b, or a and b noe ndir ncpab ncpba nsab nsba lh xxx ll x xx hx xx } transfer stored data to a or b noe ndir ncpab ncpba nsab nsba l l x h | l x h l h h | l x h x abab ab ab sh00028
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 6 logic diagram 1d c1 q nb1 nb2 nb3 nb4 nb5 nb6 nb7 na1 na2 na3 na4 na5 na6 na7 detail a x 7 noe ndir ncpba nsba ncpab nsab nb0 1d c1 q na0 1 of 16 channels sh00029 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i out dc out p ut current output in low state 128 ma i out dc out ut current output in high state 64 ma t stg storage temperature range 65 to 150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 7 recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 10 ns/v t amb operating free-air temperature range 40 +85 c dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5v; i ik = 18ma 0.9 1.2 1.2 v v cc = 4.5v; i oh = 3ma; v i = v il or v ih 2.5 2.9 2.5 v v oh high-level output voltage v cc = 5.0v; i oh = 3ma; v i = v il or v ih 3.0 3.4 3.0 v v cc = 4.5v; i oh = 32ma; v i = v il or v ih 2.0 2.4 2.0 v v ol low-level output voltage v cc = 4.5v; i ol = 64ma; v i = v il or v ih 0.35 0.55 0.55 v v rst power-up output voltage 3 v cc = 5.5v; i o = 1ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage v cc =55v ; v i = gnd or 5 5v control 001 10 10 m a i i g current v cc = 5 . 5v v i = gnd or 5 . 5v pins 0 . 01 1 . 0 1 . 0 m a bus hold current a or b v cc = 4.5v; v i = 0.8v 35 35 i hold b us h o ld curren t a or b ports 5 74abth16646 v cc = 4.5v; v i = 2.0v 75 75 m a ports 74abth16646 v cc = 5.5v; v i = 0 to 5.5v 800 i off power-off leakage current v cc = 0.0v; v o = 4.5v; v i = 0.0v or 5.5v 2.0 100 100 m a i pu/pd power-up/down 3-state output current 4 v cc = 2.1v; v o = 0.0v or v cc ; v i = gnd or v cc ; oe/oe = x 1.0 50 50 m a i ih + i ozh 3-state output high current v cc = 5.5v; v o = 5.5v; v i = v il or v ih 1.0 10 10 m a i il + i ozl 3-state output low current v cc = 5.5v; v o = 0.0v; v i = v il or v ih 1.0 10 10 m a i cex output high leakage current v cc = 5.5v; v o = 5.5v; v i = gnd or v cc 5.0 50 50 m a i o output current 1 v cc = 5.5v; v o = 2.5v 50 80 180 50 180 ma i cch v cc = 5.5v; outputs high, v i = gnd or v cc 0.55 2 2 ma i ccl quiescent supply current v cc = 5.5v; outputs low, v i = gnd or v cc 9 19 19 ma i ccz v cc = 5.5v; outputs 3state; v i = gnd or v cc 0.55 2 2 ma d i cc additional supply current per input pin 2 74ABT16646 v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 5.0 50 50 m a d i cc additional supply current per input pin 2 74abth16646 v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 200 500 500 m a notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. this parameter is valid for any v cc between 0v and 2.0v, with a transition time of up to 100msec. from v cc = 21.v to v cc = 5v 10% a transition time of up to 100 m sec is permitted. 5. this is the bus hold overdrive current required to force the input to the opposite logic state.
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 8 ac characteristics gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = -40 to +85 o c v cc = +5.0v 0.5v unit min typ max min max f max maximum clock frequency 1 125 125 mhz t plh t phl propagation delay ncpab to nbx or ncpba to nax 1 1.5 1.5 3.3 2.7 4.0 4.1 1.5 1.5 4.9 4.7 ns t plh t phl propagation delay nax to nbx or nbx to nax 2 1.0 1.0 2.3 2.0 3.2 4.1 1.0 1.0 3.9 4.6 ns t plh t phl propagation delay nsab to nbx or nsba to nax 2, 3 1.0 1.0 3.1 2.7 4.3 4.3 1.0 1.0 5.0 5.0 ns t pzh t pzl output enable time noe to nax or nbx 5, 6 1.0 1.5 3.2 3.3 4.6 4.9 1.0 1.5 5.5 5.7 ns t phz t plz output disable time noe to nax or nbx 5, 6 1.5 1.5 3.5 2.7 4.9 4.1 1.5 1.5 5.4 4.5 ns t pzh t pzl output enable time ndir to nax or nbx 5, 6 1.0 1.5 4.1 4.3 4.8 4.8 1.0 1.5 5.4 5.6 ns t phz t plz output disable time ndir to nax or nbx 5, 6 2.0 1.5 3.6 2.7 5.7 5.1 2.0 1.5 6.7 5.9 ns ac setup requirements gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = -40 to +85 o c v cc = +5.0v 0.5v unit min typ min t s (h) t s (l) setup time nax to ncpab, nbx to ncpba 4 2.0 1.5 1.0 0.8 2.0 1.5 ns t h (h) t h (l) hold time nax to ncpab, nbx to ncpba 4 1.5 1.0 0.0 0.7 1.5 1.0 ns t w (h) t w (l) pulse width, high or low ncpab or ncpba 1 4.5 3.0 2.5 2.0 4.5 3.0 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v v m v m v m v m v m 1/f max t w (h) t w (l) t phl t plh ncpba or ncpab nax or nbx sh00030 0v 3.0v or v cc whichever is less v oh v ol waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency nsba or nsab v m t plh t phl v m v m v m nax or nbx nax or nbx nax or nbx sh00031 3.0v or v cc 0v v oh v ol waveform 2. propagation delay, nsab to nbx or nsba to nax, nax to nbx or nbx to nax
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 9 ac waveforms (continued) v m = 1.5v, v in = gnd to 3.0v v m t phl t plh v m v m v m nsba or nsab nax or nbx sh00032 3.0v or v cc 0v v oh v ol waveform 3. propagation delay, nsba to nax or nsab to nbx v m nax or nbx v m v m v m v m v m ncpba or ncpab t s (h) t h (h) t s (l) t h (l) sh00033 note: the shaded areas indicate when the input is permitted to change for predictable output performance. 3.0v or v cc 0v 3.0v or v cc 0v waveform 4. data setup and hold times noe , ndir v m t pzh t phz 0v v y v m v m nax or nbx ndir v oh sh00034 0v 3.0v or v cc whichever is less waveform 5. 3state output enable time to high level and output disable time from high level t pzl t plz 0v v x v m v m v m noe , ndir nax or nbx ndir sh00035 v ol 3.0v or v cc 0v 3.0v or v cc waveform 6. 3state output enable time to low level and output disable time from low level test circuit and waveforms pulse generator r t v in d.u.t. v out r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt/h16 3.0v 1mhz 500ns 2.5ns 2.5ns switch position test switch t plz closed t pzl closed all other open sa00018 c l
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 10 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) 1998 feb 27 11 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1mm sot364-1
philips semiconductors product specification 74ABT16646 74abth16646 16-bit bus transceiver/register (3-state) yyyy mmm dd 12 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number: 9397-750-03498
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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